VLSI Implementation of Ternary Gates MultiValue System
- Author Mohamed Ibrahim. J
- Co-Author Dr. K. Somu
- DOI 10.17605/O
- Country : India
- Subject : Engineering
Keywords : VLSI, Multi Valued Logic, Ternary, Logic Gates
Abstract
CMOS logic is taken into account for implementation of solely binary logic, because the circuit complexness is increasing, the interconnection in binary occupies massive space on VLSI chip & so, degrading the performance. MVL (Multi valued logic) is taken into account as resolution to the current issue. A Ternary logic or three-valued logic is taken into account as best base of many MVL systems.
The planned GATES area unit styled & simulated with the assistance of Tanner EDA tool and layout design victimization VLSI CMOS technology. Planned system: In style of digital systems, the electrical converter, NOR gate & NAND gates area unit thought-about to be building blocks. The most objective is to reduce the facility consumption & propagation delay time thereby reducing the quantity of electronic transistor.
In the planned styles, the smaller single provide voltage & MOSFETs with smaller threshold voltage area unit used. 3 logic levels area unit drawn by states zero, 1, a pair of with potential (0v), (0.5v), & +Vcc (+1v) severally. Within the planned styles, these output transmission gates/pull up transistors area unit eliminated from inverters, thereby reducing the part count.
Use of single power provide to implement ternary logic gates has result in important reduction in overall power dissipation & rising the transition time Considering the varied benefits of the MVL, the acceptable style of MVL logic gates is vital so it'll result in the more development and its application in this area.
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